Techniques for Reducing Read Latency of Core Bus Wrappers.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/LyseckyVG00
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Techniques for Reducing Read Latency of Core Bus Wrappers.
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Cores, system-on-a-chip, interfacing, on-chip bus, intellectual property, design reuse, bus wrapper
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Techniques for Reducing Read Latency of Core Bus Wrappers.
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