[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/MiryalaMCMP13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mehrdad_Montazeri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sandeep_Miryala>
foaf:homepage <http://dx.doi.org/doi.org%2F10.7873%2FDATE.2013.185>
foaf:homepage <https://doi.org/10.7873/DATE.2013.185>
dc:identifier DBLP conf/date/MiryalaMCMP13 (xsd:string)
dc:identifier DOI doi.org%2F10.7873%2FDATE.2013.185 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
rdfs:label A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mehrdad_Montazeri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sandeep_Miryala>
swrc:pages 877-880 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/2013>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/date/MiryalaMCMP13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/date/MiryalaMCMP13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/date/date2013.html#MiryalaMCMP13>
rdfs:seeAlso <https://doi.org/10.7873/DATE.2013.185>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:title A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document