ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/MullerBJ06
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ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
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ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.
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