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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/PanYZS10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fan_Yang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaoda_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yangfeng_Su>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDATE.2010.5457083>
foaf:homepage <https://doi.org/10.1109/DATE.2010.5457083>
dc:identifier DBLP conf/date/PanYZS10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDATE.2010.5457083 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fan_Yang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaoda_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuan_Zeng_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yangfeng_Su>
swrc:pages 1673-1676 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/date/PanYZS10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/date/PanYZS10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/date/date2010.html#PanYZS10>
rdfs:seeAlso <https://doi.org/10.1109/DATE.2010.5457083>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:title An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document