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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/PullelaPDV98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Dharchoudhury>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gopal_Vija>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajendran_Panda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDATE.1998.656001>
foaf:homepage <https://doi.org/10.1109/DATE.1998.656001>
dc:identifier DBLP conf/date/PullelaPDV98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDATE.1998.656001 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label CMOS Combinational Circuit Sizing by Stage-wise Tapering. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Dharchoudhury>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gopal_Vija>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajendran_Panda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
swrc:pages 985-986 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/date/PullelaPDV98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/date/PullelaPDV98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/date/date1998.html#PullelaPDV98>
rdfs:seeAlso <https://doi.org/10.1109/DATE.1998.656001>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:subject Transistor sizing, tapering, resynthesis (xsd:string)
dc:title CMOS Combinational Circuit Sizing by Stage-wise Tapering. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document