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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/RanjanVASVG04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anuradha_Agarwal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Georges_G._E._Gielen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hemanth_Sampath>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mukesh_Ranjan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wim_Verhaegen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDATE.2004.1268911>
foaf:homepage <https://doi.org/10.1109/DATE.2004.1268911>
dc:identifier DBLP conf/date/RanjanVASVG04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDATE.2004.1268911 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anuradha_Agarwal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Georges_G._E._Gielen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hemanth_Sampath>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mukesh_Ranjan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wim_Verhaegen>
swrc:pages 604-609 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/2004>
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rdfs:seeAlso <https://doi.org/10.1109/DATE.2004.1268911>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:title Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document