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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/SalapuraG98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Gschwind>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Valentina_Salapura>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDATE.1998.655961>
foaf:homepage <https://doi.org/10.1109/DATE.1998.655961>
dc:identifier DBLP conf/date/SalapuraG98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDATE.1998.655961 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label Hardware/Software Co-Design of a Fuzzy RISC Processor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Gschwind>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Valentina_Salapura>
swrc:pages 875-882 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/date/SalapuraG98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/date/SalapuraG98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/date/date1998.html#SalapuraG98>
rdfs:seeAlso <https://doi.org/10.1109/DATE.1998.655961>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:subject hardware/software co-evaluation, hardware/software co-design, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, application specific instruction set processor (ASIP), subword parallelism, VHDL, logic synthesis, instruction set definition, instruction set architecture, performance evaluation (xsd:string)
dc:title Hardware/Software Co-Design of a Fuzzy RISC Processor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document