Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/WangAZ98
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/date/WangAZ98
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jing_Zeng
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Li-C._Wang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Magdy_S._Abadir
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FDATE.1998.655867
>
foaf:
homepage
<
https://doi.org/10.1109/DATE.1998.655867
>
dc:
identifier
DBLP conf/date/WangAZ98
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FDATE.1998.655867
(xsd:string)
dcterms:
issued
1998
(xsd:gYear)
rdfs:
label
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jing_Zeng
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Li-C._Wang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Magdy_S._Abadir
>
swrc:
pages
273-277
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/date/1998
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/date/WangAZ98/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/date/WangAZ98
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/date/date1998.html#WangAZ98
>
rdfs:
seeAlso
<
https://doi.org/10.1109/DATE.1998.655867
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/date
>
dc:
subject
Design Error Models, Design Validation, Verification
(xsd:string)
dc:
title
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document