Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/YeCFCNC99
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Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.
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Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.
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