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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ddecs/PodivinskyiCK15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jakub_Podivinsky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcela_Simkov%E2%88%9A%C2%B0>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ondrej_Cekan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zdenek_Kot%E2%88%9A%C2%B0sek>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDDECS.2015.33>
foaf:homepage <https://doi.org/10.1109/DDECS.2015.33>
dc:identifier DBLP conf/ddecs/PodivinskyiCK15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDDECS.2015.33 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label FPGA Prototyping and Accelerated Verification of ASIPs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jakub_Podivinsky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcela_Simkov%E2%88%9A%C2%B0>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ondrej_Cekan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zdenek_Kot%E2%88%9A%C2%B0sek>
swrc:pages 145-148 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ddecs/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ddecs/PodivinskyiCK15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ddecs/PodivinskyiCK15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ddecs/ddecs2015.html#PodivinskyiCK15>
rdfs:seeAlso <https://doi.org/10.1109/DDECS.2015.33>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ddecs>
dc:title FPGA Prototyping and Accelerated Verification of ASIPs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document