Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/ddecs/Strnadel21>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Josef_Strnadel>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FDDECS52668.2021.9417069>
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dc:identifier	DBLP conf/ddecs/Strnadel21 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FDDECS52668.2021.9417069 (xsd:string)
dcterms:issued	2021 (xsd:gYear)
rdfs:label	Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Josef_Strnadel>
swrc:pages	111-114 (xsd:string)
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owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/ddecs/Strnadel21>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/ddecs/ddecs2021.html#Strnadel21>
rdfs:seeAlso	<https://doi.org/10.1109/DDECS52668.2021.9417069>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/ddecs>
dc:title	Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. (xsd:string)
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rdf:type	swrc:InProceedings
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