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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dft/GagnonSMT97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Claude_Thibeault>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michel_Meunier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yves_Gagnon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDFTVS.1997.628321>
foaf:homepage <https://doi.org/10.1109/DFTVS.1997.628321>
dc:identifier DBLP conf/dft/GagnonSMT97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDFTVS.1997.628321 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Claude_Thibeault>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michel_Meunier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yves_Gagnon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
swrc:pages 157-165 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dft/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dft/GagnonSMT97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dft/GagnonSMT97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dft/dft1997.html#GagnonSMT97>
rdfs:seeAlso <https://doi.org/10.1109/DFTVS.1997.628321>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dft>
dc:subject integrated circuit testing; defect-tolerant circuit; redundancy; cost model; yield; fault tolerant circuit; manufacturing; contamination; reconfiguration; wafer test; figure of merit; silicon chip; integrated circuit (xsd:string)
dc:title Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document