Mitigation of the impact of across chip systematic process variation using a novel system level design.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dft/GhoshalSYZKP21
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/dft/GhoshalSYZKP21
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Anil_Kumar_Kandala
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Nabanita_Ghoshal
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Narendra_Kumar_Pulipati
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Santosh_Yachareni
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shidong_Zhou
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sree_Rama_K._C._Saraswatula
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FDFT52944.2021.9568294
>
foaf:
homepage
<
https://doi.org/10.1109/DFT52944.2021.9568294
>
dc:
identifier
DBLP conf/dft/GhoshalSYZKP21
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FDFT52944.2021.9568294
(xsd:string)
dcterms:
issued
2021
(xsd:gYear)
rdfs:
label
Mitigation of the impact of across chip systematic process variation using a novel system level design.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Anil_Kumar_Kandala
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Nabanita_Ghoshal
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Narendra_Kumar_Pulipati
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Santosh_Yachareni
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shidong_Zhou
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sree_Rama_K._C._Saraswatula
>
swrc:
pages
1-4
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/dft/2021
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/dft/GhoshalSYZKP21/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/dft/GhoshalSYZKP21
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/dft/dft2021.html#GhoshalSYZKP21
>
rdfs:
seeAlso
<
https://doi.org/10.1109/DFT52944.2021.9568294
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/dft
>
dc:
title
Mitigation of the impact of across chip systematic process variation using a novel system level design.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document