Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dft/OttaviCCPRS01
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Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.
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fault tolerance, finite state machine, SSMM, self checking, VHDL, signature analysis
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Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.
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