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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dft/TakanamiH97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDFTVS.1997.628328>
foaf:homepage <https://doi.org/10.1109/DFTVS.1997.628328>
dc:identifier DBLP conf/dft/TakanamiH97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDFTVS.1997.628328 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
swrc:pages 218-226 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dft/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dft/TakanamiH97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dft/TakanamiH97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dft/dft1997.html#TakanamiH97>
rdfs:seeAlso <https://doi.org/10.1109/DFTVS.1997.628328>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dft>
dc:subject VLSI; self-reconstruction; mesh-connected processor arrays; digital neural circuits; Hopfield-type neural algorith; 1 1/2 -track switches; compensation paths; subcircuits; stable state; parallel state transitions (xsd:string)
dc:title Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document