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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/BabuICC03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahsan_Raja_Chowdhury>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hafiz_Md._Hasan_Babu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Md._Rafiqul_Islam_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Syed_Mostahed_Ali_Chowdhury>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD.2003.1231899>
foaf:homepage <https://doi.org/10.1109/DSD.2003.1231899>
dc:identifier DBLP conf/dsd/BabuICC03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD.2003.1231899 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Reversible Logic Synthesis for Minimization of Full-Adder Circuit. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahsan_Raja_Chowdhury>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hafiz_Md._Hasan_Babu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Md._Rafiqul_Islam_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Syed_Mostahed_Ali_Chowdhury>
swrc:pages 50-54 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dsd/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dsd/BabuICC03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dsd/BabuICC03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2003.html#BabuICC03>
rdfs:seeAlso <https://doi.org/10.1109/DSD.2003.1231899>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title Reversible Logic Synthesis for Minimization of Full-Adder Circuit. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document