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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/DangerYGMSSMN18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abdelmalek_Si-Merabet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean-Luc_Danger>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazuo_Sakiyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Makoto_Nagata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Noriyuki_Miura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Risa_Yashiro>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tarik_Graba>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yves_Mathieu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD.2018.00090>
foaf:homepage <https://doi.org/10.1109/DSD.2018.00090>
dc:identifier DBLP conf/dsd/DangerYGMSSMN18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD.2018.00090 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abdelmalek_Si-Merabet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean-Luc_Danger>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazuo_Sakiyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Makoto_Nagata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Noriyuki_Miura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Risa_Yashiro>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tarik_Graba>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yves_Mathieu>
swrc:pages 508-515 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dsd/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dsd/DangerYGMSSMN18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dsd/DangerYGMSSMN18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2018.html#DangerYGMSSMN18>
rdfs:seeAlso <https://doi.org/10.1109/DSD.2018.00090>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document