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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/GokulanMV20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Akshay_Muraleedharan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuruvilla_Varghese>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/T._Gokulan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD51259.2020.00062>
foaf:homepage <https://doi.org/10.1109/DSD51259.2020.00062>
dc:identifier DBLP conf/dsd/GokulanMV20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD51259.2020.00062 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Akshay_Muraleedharan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuruvilla_Varghese>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/T._Gokulan>
swrc:pages 340-343 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dsd/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dsd/GokulanMV20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dsd/GokulanMV20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2020.html#GokulanMV20>
rdfs:seeAlso <https://doi.org/10.1109/DSD51259.2020.00062>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document