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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/MaciiBCMP08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Let%E2%88%9A%E2%89%A0cia_Maria_Veiras_Bolzani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD.2008.90>
foaf:homepage <https://doi.org/10.1109/DSD.2008.90>
dc:identifier DBLP conf/dsd/MaciiBCMP08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD.2008.90 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Let%E2%88%9A%E2%89%A0cia_Maria_Veiras_Bolzani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
swrc:pages 298-303 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dsd/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dsd/MaciiBCMP08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dsd/MaciiBCMP08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2008.html#MaciiBCMP08>
rdfs:seeAlso <https://doi.org/10.1109/DSD.2008.90>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document