Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dsd/RajiGP15
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Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations.
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Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations.
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