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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/RavindraS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._V._R._Ravindra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._B._Srinivas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD.2007.4341488>
foaf:homepage <https://doi.org/10.1109/DSD.2007.4341488>
dc:identifier DBLP conf/dsd/RavindraS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD.2007.4341488 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._V._R._Ravindra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._B._Srinivas>
swrc:pages 325-330 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2007.html#RavindraS07>
rdfs:seeAlso <https://doi.org/10.1109/DSD.2007.4341488>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document