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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dsd/ZhangRM06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aarne_M%E2%88%9A%C2%A7mmel%E2%88%9A%C2%A7>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jussi_Roivainen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yan_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDSD.2006.32>
foaf:homepage <https://doi.org/10.1109/DSD.2006.32>
dc:identifier DBLP conf/dsd/ZhangRM06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDSD.2006.32 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Clock-Gating in FPGAs: A Novel and Comparative Evaluation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aarne_M%E2%88%9A%C2%A7mmel%E2%88%9A%C2%A7>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jussi_Roivainen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yan_Zhang>
swrc:pages 584-590 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dsd/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dsd/ZhangRM06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dsd/ZhangRM06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dsd/dsd2006.html#ZhangRM06>
rdfs:seeAlso <https://doi.org/10.1109/DSD.2006.32>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dsd>
dc:title Clock-Gating in FPGAs: A Novel and Comparative Evaluation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document