Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dtis/ChvalaNMPDS19
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/dtis/ChvalaNMPDS19
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ales_Chv%E2%88%9A%C2%B0la
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alexander_Satka
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Donoval
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Juraj_Marek
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Juraj_Priesol
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Luk%E2%88%9A%C2%B0s_Nagy
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FDTIS.2019.8735087
>
foaf:
homepage
<
https://doi.org/10.1109/DTIS.2019.8735087
>
dc:
identifier
DBLP conf/dtis/ChvalaNMPDS19
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FDTIS.2019.8735087
(xsd:string)
dcterms:
issued
2019
(xsd:gYear)
rdfs:
label
Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ales_Chv%E2%88%9A%C2%B0la
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alexander_Satka
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Donoval
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Juraj_Marek
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Juraj_Priesol
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Luk%E2%88%9A%C2%B0s_Nagy
>
swrc:
pages
1-4
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/dtis/2019
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/dtis/ChvalaNMPDS19/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/dtis/ChvalaNMPDS19
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/dtis/dtis2019.html#ChvalaNMPDS19
>
rdfs:
seeAlso
<
https://doi.org/10.1109/DTIS.2019.8735087
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/dtis
>
dc:
title
Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document