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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dtis/Dasygenis14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Minas_Dasygenis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDTIS.2014.6850659>
foaf:homepage <https://doi.org/10.1109/DTIS.2014.6850659>
dc:identifier DBLP conf/dtis/Dasygenis14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDTIS.2014.6850659 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Minas_Dasygenis>
swrc:pages 1-2 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dtis/dtis2014.html#Dasygenis14>
rdfs:seeAlso <https://doi.org/10.1109/DTIS.2014.6850659>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dtis>
dc:title A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document