A time digitizer based on multiphase clock implemented in FPGA device.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ebccsp/KwiatkowskiSJR16
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/ebccsp/KwiatkowskiSJR16
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Krzysztof_Rozyc
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Pawel_Kwiatkowski
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ryszard_Szplet
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zbigniew_Jachna
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FEBCCSP.2016.7605280
>
foaf:
homepage
<
https://doi.org/10.1109/EBCCSP.2016.7605280
>
dc:
identifier
DBLP conf/ebccsp/KwiatkowskiSJR16
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FEBCCSP.2016.7605280
(xsd:string)
dcterms:
issued
2016
(xsd:gYear)
rdfs:
label
A time digitizer based on multiphase clock implemented in FPGA device.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Krzysztof_Rozyc
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Pawel_Kwiatkowski
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ryszard_Szplet
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zbigniew_Jachna
>
swrc:
pages
1-6
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/ebccsp/2016
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/ebccsp/KwiatkowskiSJR16/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/ebccsp/KwiatkowskiSJR16
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/ebccsp/ebccsp2016.html#KwiatkowskiSJR16
>
rdfs:
seeAlso
<
https://doi.org/10.1109/EBCCSP.2016.7605280
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/ebccsp
>
dc:
title
A time digitizer based on multiphase clock implemented in FPGA device.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document