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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francisco_J._Cazorla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaume_Abella_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juan_M._Reina>
foaf:homepage <http://dx.doi.org/doi.org%2F10.4230%2FLIPIcs.ECRTS.2021.3>
foaf:homepage <https://doi.org/10.4230/LIPIcs.ECRTS.2021.3>
dc:identifier DBLP conf/ecrts/Serrano-CasesR021 (xsd:string)
dc:identifier DOI doi.org%2F10.4230%2FLIPIcs.ECRTS.2021.3 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alejandro_Serrano-Cases>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaume_Abella_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juan_M._Reina>
swrc:pages 3:1-3:26 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.4230/LIPIcs.ECRTS.2021.3>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ecrts>
dc:title Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document