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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/elinfocom/ChangC19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guan-Jhen_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yun-Nan_Chang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FELINFOCOM.2019.8706444>
foaf:homepage <https://doi.org/10.23919/ELINFOCOM.2019.8706444>
dc:identifier DBLP conf/elinfocom/ChangC19 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FELINFOCOM.2019.8706444 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guan-Jhen_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yun-Nan_Chang>
swrc:pages 1-3 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/elinfocom/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/elinfocom/ChangC19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/elinfocom/ChangC19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/elinfocom/iceic2019.html#ChangC19>
rdfs:seeAlso <https://doi.org/10.23919/ELINFOCOM.2019.8706444>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/elinfocom>
dc:title Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document