Modeling a system controller for timing analysis. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/emsoft/Thesing06>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Stephan_Thesing>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1176887.1176929>
foaf:homepage	<https://doi.org/10.1145/1176887.1176929>
dc:identifier	DBLP conf/emsoft/Thesing06 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1176887.1176929 (xsd:string)
dcterms:issued	2006 (xsd:gYear)
rdfs:label	Modeling a system controller for timing analysis. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Stephan_Thesing>
swrc:pages	292-300 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/emsoft/2006>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/emsoft/Thesing06/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/emsoft/Thesing06>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/emsoft/emsoft2006.html#Thesing06>
rdfs:seeAlso	<https://doi.org/10.1145/1176887.1176929>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/emsoft>
dc:subject	VHDL, WCET, aiT, avionics, peripherals, static analysis, timing analysis, verification, worst-case execution time (xsd:string)
dc:title	Modeling a system controller for timing analysis. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document