Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FESSCIRC.2013.6649108>
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rdfs:label	Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. (xsd:string)
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dc:title	Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. (xsd:string)
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