A DDR3/4 memory link TX supporting 24-40 ‚Ą¶, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:title	A DDR3/4 memory link TX supporting 24-40 ‚Ą¶, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. (xsd:string)
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