A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/esscirc/YuanWWZWJZW15>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chun_Zhang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Liji_Wu>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Peng_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shuai_Yuan_0005>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Wen_Jia>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xuqiang_Zheng>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zhihua_Wang_0001>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Ziqiang_Wang>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FESSCIRC.2015.7313849>
foaf:homepage	<https://doi.org/10.1109/ESSCIRC.2015.7313849>
dc:identifier	DBLP conf/esscirc/YuanWWZWJZW15 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FESSCIRC.2015.7313849 (xsd:string)
dcterms:issued	2015 (xsd:gYear)
rdfs:label	A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Chun_Zhang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Liji_Wu>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Peng_Wang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Shuai_Yuan_0005>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Wen_Jia>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Xuqiang_Zheng>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Zhihua_Wang_0001>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Ziqiang_Wang>
swrc:pages	144-147 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/esscirc/2015>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/esscirc/YuanWWZWJZW15/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/esscirc/YuanWWZWJZW15>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/esscirc/esscirc2015.html#YuanWWZWJZW15>
rdfs:seeAlso	<https://doi.org/10.1109/ESSCIRC.2015.7313849>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/esscirc>
dc:title	A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document