Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Doris_Schmitt-Landsiedel>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Eric_Liau>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FETW.2003.1231676>
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dc:identifier	DBLP conf/ets/LiauS03 (xsd:string)
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dcterms:issued	2003 (xsd:gYear)
rdfs:label	Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. (xsd:string)
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dc:title	Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. (xsd:string)
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