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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ets/SisejkovicMLAK19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dominik_Sisejkovic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Farhad_Merchant>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerd_Ascheid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rainer_Leupers>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sascha_Kegreiss>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FETS.2019.8791528>
foaf:homepage <https://doi.org/10.1109/ETS.2019.8791528>
dc:identifier DBLP conf/ets/SisejkovicMLAK19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FETS.2019.8791528 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dominik_Sisejkovic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Farhad_Merchant>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerd_Ascheid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rainer_Leupers>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sascha_Kegreiss>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ets/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ets/SisejkovicMLAK19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ets/SisejkovicMLAK19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ets/ets2019.html#SisejkovicMLAK19>
rdfs:seeAlso <https://doi.org/10.1109/ETS.2019.8791528>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ets>
dc:title Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document