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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kin-Hong_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwong-Sak_Leung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sin_Man_Cheang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wai_Shing_Lau>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-31989-4%5F15>
foaf:homepage <https://doi.org/10.1007/978-3-540-31989-4_15>
dc:identifier DBLP conf/eurogp/LauLLLC05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-31989-4%5F15 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Multi-logic-Unit Processor: A Combinational Logic Circuit Evaluation Engine for Genetic Parallel Programming. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gang_Li_0016>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kin-Hong_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwong-Sak_Leung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sin_Man_Cheang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wai_Shing_Lau>
swrc:pages 167-177 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/eurogp/eurogp2005.html#LauLLLC05>
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dc:title Multi-logic-Unit Processor: A Combinational Logic Circuit Evaluation Engine for Genetic Parallel Programming. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document