High performance in tree-based parallel architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/AnconaRZ97
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1997
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High performance in tree-based parallel architectures.
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performance evaluation; high performance; tree-based parallel architectures; integrated schema; complex node; dual-port memory; bidirectional high-speed communication link; tree-structured processor hierarchies; optimality; connectivity; memory speed; transputers; experimental development; associative models
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High performance in tree-based parallel architectures.
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