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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/euromicro/CollinsS96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gordon_B._Steven>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roger_Collins>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FEURMIC.1996.546492>
foaf:homepage <https://doi.org/10.1109/EURMIC.1996.546492>
dc:identifier DBLP conf/euromicro/CollinsS96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FEURMIC.1996.546492 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Instruction Scheduling for a Superscalar Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gordon_B._Steven>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roger_Collins>
swrc:pages 643-650 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/euromicro/CollinsS96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/euromicro/CollinsS96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/euromicro/euromicro1996.html#CollinsS96>
rdfs:seeAlso <https://doi.org/10.1109/EURMIC.1996.546492>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/euromicro>
dc:subject performance evaluation; superscalar architecture; superscalar processors; compile-time instruction scheduling; conditional group scheduler; HSA processor model; guarded instruction execution; instruction squashing; instruction buffer; functional units; branch instructions (xsd:string)
dc:title Instruction Scheduling for a Superscalar Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document