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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/euromicro/Flynn97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_J._Flynn>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FEURMIC.1997.617171>
foaf:homepage <https://doi.org/10.1109/EURMIC.1997.617171>
dc:identifier DBLP conf/euromicro/Flynn97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FEURMIC.1997.617171 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label What's ahead in computer design? (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_J._Flynn>
swrc:pages 4- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/euromicro/Flynn97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/euromicro/Flynn97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/euromicro/euromicro1997.html#Flynn97>
rdfs:seeAlso <https://doi.org/10.1109/EURMIC.1997.617171>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/euromicro>
dc:subject logic design; computer design; CMOS technology; lithography; die area improvement; multiprocessors; very high level superscalar processors; VLIW; very large cache; pin bandwidth; scalability; silicon area; cycle time; cache size; processor complexity; instruction level parallelism (xsd:string)
dc:title What's ahead in computer design? (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document