RT level testability analysis to reduce test application time.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/KotasekZ97
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RT level testability analysis to reduce test application time.
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logic testing; register transfer level testability analysis; test application time reduction; RTL element classification; RTL circuit transformation; labelled directed graph; PROLOG environment; implementation principles
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RT level testability analysis to reduce test application time.
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