Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/euromicro/Lin00>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Rong_Lin>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FEURMIC.2000.874531>
foaf:homepage	<https://doi.org/10.1109/EURMIC.2000.874531>
dc:identifier	DBLP conf/euromicro/Lin00 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FEURMIC.2000.874531 (xsd:string)
dcterms:issued	2000 (xsd:gYear)
rdfs:label	Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Rong_Lin>
swrc:pages	2456-2463 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/2000>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/euromicro/Lin00/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/euromicro/Lin00>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/euromicro/euromicro2000.html#Lin00>
rdfs:seeAlso	<https://doi.org/10.1109/EURMIC.2000.874531>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/euromicro>
dc:subject	Arithmetic circuit, parallel counter and compressor, partial product reduction, low power high performance CMOS circuit design, VLSI design (xsd:string)
dc:title	Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document