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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/euromicro/PandeySW96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kothanda_R._Subramanian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_A._Wilsey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sheetanshu_L._Pandey>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FEURMIC.1996.546379>
foaf:homepage <https://doi.org/10.1109/EURMIC.1996.546379>
dc:identifier DBLP conf/euromicro/PandeySW96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FEURMIC.1996.546379 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A Semantic Model of VHDL for Validating Rewriting Algebras. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kothanda_R._Subramanian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_A._Wilsey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sheetanshu_L._Pandey>
swrc:pages 167-176 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/euromicro/PandeySW96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/euromicro/PandeySW96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/euromicro/euromicro1996.html#PandeySW96>
rdfs:seeAlso <https://doi.org/10.1109/EURMIC.1996.546379>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/euromicro>
dc:subject hardware description languages; semantic model; VHDL; rewriting algebras validation; formal model; dynamic semantics; interval temporal logic; declarative style; process-folding; CAD tool optimization (xsd:string)
dc:title A Semantic Model of VHDL for Validating Rewriting Algebras. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document