A Semantic Model of VHDL for Validating Rewriting Algebras.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/euromicro/PandeySW96
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1996
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A Semantic Model of VHDL for Validating Rewriting Algebras.
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hardware description languages; semantic model; VHDL; rewriting algebras validation; formal model; dynamic semantics; interval temporal logic; declarative style; process-folding; CAD tool optimization
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A Semantic Model of VHDL for Validating Rewriting Algebras.
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