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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/europar/WangWWL08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dong_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qigang_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Wei>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-85451-7%5F20>
foaf:homepage <https://doi.org/10.1007/978-3-540-85451-7_20>
dc:identifier DBLP conf/europar/WangWWL08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-85451-7%5F20 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dong_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qigang_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Wei>
swrc:pages 182-191 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/europar/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/europar/WangWWL08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/europar/WangWWL08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/europar/europar2008.html#WangWWL08>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-85451-7_20>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/europar>
dc:subject Memory architecture; Performance model; Trace-driven simulation (xsd:string)
dc:title Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document