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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/facs2/BijoJPT17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Einar_Broch_Johnsen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ka_I_Pun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shiji_Bijo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Silvia_Lizeth_Tapia_Tarifa>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-68034-7%5F4>
foaf:homepage <https://doi.org/10.1007/978-3-319-68034-7_4>
dc:identifier DBLP conf/facs2/BijoJPT17 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-68034-7%5F4 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Einar_Broch_Johnsen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ka_I_Pun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shiji_Bijo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Silvia_Lizeth_Tapia_Tarifa>
swrc:pages 58-77 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/facs2/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/facs2/BijoJPT17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/facs2/BijoJPT17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/facs2/facs2017.html#BijoJPT17>
rdfs:seeAlso <https://doi.org/10.1007/978-3-319-68034-7_4>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/facs2>
dc:title A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document