A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fccm/BenkridBC03a
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/fccm/BenkridBC03a
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Abdsamad_Benkrid
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Danny_Crookes
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Khaled_Benkrid
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FFPGA.2003.1227267
>
foaf:
homepage
<
https://doi.org/10.1109/FPGA.2003.1227267
>
dc:
identifier
DBLP conf/fccm/BenkridBC03a
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FFPGA.2003.1227267
(xsd:string)
dcterms:
issued
2003
(xsd:gYear)
rdfs:
label
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Abdsamad_Benkrid
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Danny_Crookes
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Khaled_Benkrid
>
swrc:
pages
273-275
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/fccm/2003
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/fccm/BenkridBC03a/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/fccm/BenkridBC03a
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/fccm/fccm2003.html#BenkridBC03a
>
rdfs:
seeAlso
<
https://doi.org/10.1109/FPGA.2003.1227267
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/fccm
>
dc:
title
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document