On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fccm/CongP97
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On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.
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On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.
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