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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fccm/RasoulinezhadZW19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hao_Zhou_0008>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lingli_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_H._W._Leong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Seyedramin_Rasoulinezhad>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFCCM.2019.00015>
foaf:homepage <https://doi.org/10.1109/FCCM.2019.00015>
dc:identifier DBLP conf/fccm/RasoulinezhadZW19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFCCM.2019.00015 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hao_Zhou_0008>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lingli_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_H._W._Leong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Seyedramin_Rasoulinezhad>
swrc:pages 35-44 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fccm/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fccm/RasoulinezhadZW19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fccm/RasoulinezhadZW19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fccm/fccm2019.html#RasoulinezhadZW19>
rdfs:seeAlso <https://doi.org/10.1109/FCCM.2019.00015>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fccm>
dc:title PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document