Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/fccm/SimWT09
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Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
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FPGA, Reconfigurable Computing, Partial Reconfiguration, Reconfiguration Scheduling
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Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
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