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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fmcad/CabodiCPPV16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Danilo_Vendraminetto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gianpiero_Cabodi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Palena>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Camurati>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Pasini>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFMCAD.2016.7886657>
foaf:homepage <https://doi.org/10.1109/FMCAD.2016.7886657>
dc:identifier DBLP conf/fmcad/CabodiCPPV16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFMCAD.2016.7886657 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Danilo_Vendraminetto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gianpiero_Cabodi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Palena>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Camurati>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Pasini>
swrc:pages 25-32 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fmcad/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fmcad/CabodiCPPV16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fmcad/CabodiCPPV16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fmcad/fmcad2016.html#CabodiCPPV16>
rdfs:seeAlso <https://doi.org/10.1109/FMCAD.2016.7886657>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fmcad>
dc:title Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document