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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/fmcad/ChenYGC06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ching-Tsun_Chou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Gopalakrishnan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaofang_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Yang_0013>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FFMCAD.2006.28>
foaf:homepage <https://doi.org/10.1109/FMCAD.2006.28>
dc:identifier DBLP conf/fmcad/ChenYGC06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FFMCAD.2006.28 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ching-Tsun_Chou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Gopalakrishnan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaofang_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Yang_0013>
swrc:pages 81-88 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/fmcad/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/fmcad/ChenYGC06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/fmcad/ChenYGC06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/fmcad/fmcad2006.html#ChenYGC06>
rdfs:seeAlso <https://doi.org/10.1109/FMCAD.2006.28>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/fmcad>
dc:title Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document