Automatic Verification of Mixed-Level Logic Circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/F._Keith_Hanna>
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dcterms:issued	1998 (xsd:gYear)
rdfs:label	Automatic Verification of Mixed-Level Logic Circuits. (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/fmcad/fmcad1998.html#Hanna98>
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dc:title	Automatic Verification of Mixed-Level Logic Circuits. (xsd:string)
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