FPGA power reduction by guarded evaluation. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/fpga/AndersonR10>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chirag_Ravishankar>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jason_Helge_Anderson>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1723112.1723141>
foaf:homepage	<https://doi.org/10.1145/1723112.1723141>
dc:identifier	DBLP conf/fpga/AndersonR10 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1723112.1723141 (xsd:string)
dcterms:issued	2010 (xsd:gYear)
rdfs:label	FPGA power reduction by guarded evaluation. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Chirag_Ravishankar>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jason_Helge_Anderson>
swrc:pages	157-166 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/fpga/2010>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/fpga/AndersonR10/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/fpga/AndersonR10>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/fpga/fpga2010.html#AndersonR10>
rdfs:seeAlso	<https://doi.org/10.1145/1723112.1723141>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/fpga>
dc:subject	field-programmable gate arrays, fpgas, logic synthesis, low-power design, optimization, power, technology mapping (xsd:string)
dc:title	FPGA power reduction by guarded evaluation. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document